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W78ERD2/W78ERD2A Data Sheet 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 FUNCTIONAL DESCRIPTION ................................................................................................... 6 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. 8. RAM ................................................................................................................................ 6 Timers/Counters ............................................................................................................. 6 Clock ............................................................................................................................... 7 Power Management........................................................................................................ 7 Reduce EMI Emission .................................................................................................... 7 Reset............................................................................................................................... 7
SPECIAL FUNCTION REGISTER.............................................................................................. 8 PORT 4 AND BASE ADDRESS REGISTERS ......................................................................... 30 INTERRUPTS ........................................................................................................................... 32 8.1 8.2 External Interrupts 2 and 3 ........................................................................................... 32 Interrupt Priority ............................................................................................................ 32 Timer 0 and Timer 1 ..................................................................................................... 33 Timer/Counter 2............................................................................................................ 35 MODE 0 ........................................................................................................................ 38 MODE 1 ........................................................................................................................ 39 MODE 2 ........................................................................................................................ 40 MODE 3 ........................................................................................................................ 41 Framing Error Detection ............................................................................................... 42 Multi-Processor Communications................................................................................. 42 PCA Capture Mode....................................................................................................... 47 16-bit Software Timer Comparator Mode ..................................................................... 47 High Speed Output Mode ............................................................................................. 48 Pulse Width Modulator Mode ....................................................................................... 49 Watchdog Timer ........................................................................................................... 49
9.
PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 33 9.1 9.2
10.
ENHANCED FULL DUPLEX SERIAL PORT............................................................................ 38 10.1 10.2 10.3 10.4 10.5 10.6
11.
PROGRAMMABLE COUNTER ARRAY (PCA) ........................................................................ 44 11.1 11.2 11.3 11.4 11.5
12.
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT) ................... 50 Publication Release Date: February 14, 2007 Revision A10
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W78ERD2/W78ERD2A
13. 14. 15. 16. 17. 18. DUAL DPTR.............................................................................................................................. 50 TIMED-ACCESS PROTECTION .............................................................................................. 51 IN-SYSTEM PROGRAMMING (ISP) MODE ............................................................................ 53 H/W REBOOT MODE (BOOT FROM LDROM)........................................................................ 57 OPTION BITS REGISTER ........................................................................................................ 58 ELECTRICAL CHARACTERISTICS......................................................................................... 60 18.1 18.2 18.3 19. 20. Absolute Maximum Ratings .......................................................................................... 60 D.C. Characteristics...................................................................................................... 60 A.C. Characteristics ...................................................................................................... 62
TIMING WAVEFORMS ............................................................................................................. 64 TYPICAL APPLICATION CIRCUITS ........................................................................................ 66 20.1 20.2 External Program Memory and Crystal ........................................................................ 66 Expanded External Data Memory and Oscillator ......................................................... 67
21. 22.
PACKAGE DIMENSIONS ......................................................................................................... 68 APPLICATION NOTE ............................................................................................................... 70 22.1 22.2 In-System Programming (ISP) Software Examples ..................................................... 70 How to Use Programmable Counter Array................................................................... 74
23.
REVISION HISTORY ................................................................................................................ 75
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W78ERD2/W78ERD2A
1. GENERAL DESCRIPTION
The W78ERD2 is an 8-bit microcontroller which is pin- and instruction-set-compatible with the standard 80C52. The W78ERD2 contains a 64-KB Flash EPROM whose contents may be updated insystem by a loader program stored in an auxiliary, 4-KB Flash EPROM. Once the contents are confirmed, it can be protected for security. The W78ERD2 also contains 256 bytes of on-chip RAM; 1 KB of auxiliary RAM; four 8-bit, bidirectional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; and a serial port. These peripherals are all supported by nine interrupt sources with 4 levels of priority. The W78ERD2 has two power-reduction modes: idle mode and power-down mode, both of which are software-selectable. Idle mode turns off the processor clock but allows peripherals to continue operating, while power-down mode stops the crystal oscillator for minimum power consumption. Power-down mode can be activated at any time and in any state without affecting the processor.
2. FEATURES
* * * * * * * * * * * * * * * * * * * * * * 8-bit CMOS microcontroller Pin-compatible with standard 80C52 Instruction-set compatible with 80C52 Four 8-bit I/O ports; Port 0 has internal pull-up resisters enabled by software. One extra 4-bit I/O port with interrupt and chip-select functions Three 16-bit timers Programmable clock out Programmable Counter Array (PCA) with PWM, Capture, Compare and Watchdog functions 9 interrupt sources with 4 levels of priority Full-duplex serial port with framing-error detection and automatic address recognition 64-KB, in-system-programmable, Flash EPROM (AP Flash EPRAOM) 4-KB auxiliary Flash EPROM for loader program (LD Flash EPROM) 256-byte on-chip RAM 1-KB auxiliary RAM, software-selectable Software Reset 12 clocks per machine cycle operation (default). Speed up to 40 MHz. 6 clocks per machine cycle operation set by the writer. Speed up to 20 MHz. 2 DPTR registers Low EMI (inhibit ALE) Built-in power management with idle mode and power down mode Code protection Packages: -- Lead Free (RoHS) DIP 40: W78ERD2A40DL -- Lead Free (RoHS) PLCC 44: W78ERD2A40PL -- Lead Free (RoHS) PQFP 44: W78ERD2A40FL
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-Pin PLCC
T 2 E X , P 1 . 1 / I N T 3 , P 4V .D 2D
44-Pin QFP
T 2 E X , P 1 . 1 / I N T 3 , P 4V .D 2D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
P 1 . 4
P 1 . 3
P 1 . 2
T 2 , P 1 . 0
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
P 1 . 4
P 1 . 3
P 1 . 2
T 2 , P 1 . 0
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X T A L 1 V S S P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XV TS AS L 1 P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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W78ERD2/W78ERD2A
4. PIN DESCRIPTION
SYMBOL TYPE* DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute instructions in external ROM. The ROM address and data are not presented on the bus if the EA pin is high. PROGRAM STORE ENABLE: PSEN indicates external ROM data is on the Port 0 address/data bus. If internal ROM is accessed, no PSEN strobe signal is present on this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RESET: If this pin is set high for two machine cycles while the oscillator is running, the W78ERD2 is reset. CRYSTAL 1: Crystal oscillator input or external clock input. CRYSTAL 2: Crystal oscillator output. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: 8-bit, bi-directional I/O port, the same as that of the standard 80C52. Port 0 has internal pull-up resisters enabled by software. PORT 2: 8-bit, bi-directional I/O port with internal pull-ups. This port also provides the upper address bits when accessing external memory.
PSEN
OH
ALE RST XTAL1 XTAL2 VSS VDD P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.3
OH IL I O I I I/O D
I/O H PORT 1: 8-bit, bi-directional I/O port, the same as that of the standard 80C52. I/O H
I/O H PORT 3: 8-bit, bi-directional I/O port, the same as that of the standard 80C52. I/O H PORT 4: 4-bit, bi-directional I/O port with chip-select functions.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
5. FUNCTIONAL DESCRIPTION
The W78ERD2 architecture consists of a core processor that supports 111 different op-codes and references 64 KB of program space and 64 KB of data space. It is surrounded by various registers; four general-purpose I/O ports; one special-purpose, programmable, 4-bit I/O port; 256 bytes of RAM; 1 KB of auxiliary RAM (AUX-RAM); three timer/counters; a serial port; and an internal 74373 latch and 74244 buffer which can be switched to port 2. This section introduces the RAM, Timers/Counters, Clock, Power Management, Reduce EMI Emission, and Reset.
5.1
RAM
The W78ERD2 has two banks of RAM: 256 bytes of RAM and 1 KB of AUX-RAM. AUX-RAM is enabled by clearing bit 1 in the AUXR register, and it is enabled after reset. Different addresses in RAM are addressed in different ways. * RAM 00H - 7FH can be addressed directly or indirectly, as in the 8051. The address pointers are R0 and R1 of the selected bank. * RAM 80H - FFH can only be addressed indirectly, as in the 8051. The address pointers are R0 and R1 of the selected bank. * AUX-RAM 00H -3FFH is addressed indirectly in the same way external data memory is accessed with the MOVX instruction. The address pointers are R0 and R1 of the selected bank and the DPTR register. * Addresses higher than 3FFH are stored in external memory and are accessed indirectly with the MOVX instruction, as in the 8051. When AUX-RAM is enabled, the instruction "MOVX @Ri" always accesses AUX-RAM. When the W78ERD2 is executing instructions from internal program memory, accessing AUX-RAM does not affect ports P0, P2, WR or RD . For example, ANL AUXR,#11111101B MOV DPTR,#1234H MOV A,#56H MOVX @DPTR,A MOV MOV MOV XRAMAH,#02H R0,#34H A,@R0 ; Read AUX-RAM data at address 0234H ; Enable AUX-RAM
; Write 56h to address 1234H in external memory ; Only 2 LSB effective
5.2
Timers/Counters
The W78ERD2 has three timers/counters called Timer 0, Timer 1, and Timer 2. Each timer/counter consists of two 8-bit data registers: TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The operations of Timer 0 and Timer 1 are similar to those in the W78C52, and these timers are controlled by the TCON and TMOD registers.
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W78ERD2/W78ERD2A
Timer 2 is controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. In capture or auto-reload mode, RCAP2H and RCAP2L are the reload / capture registers and the clock speed is the same as that of Timers 0 and 1.
5.3
Clock
The W78ERD2 is designed for either a crystal oscillator or an external clock. The W78ERD2 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2, and a load capacitor may be connected from each pin to ground. In addition, if the crystal frequency is higher than 24 MHz, a resistor should be connected between XTAL1 and XTAL2 to provide a DC bias. An external clock is connected to pin XTAL1, while pin XTAL2 should be left disconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the logic-1 voltage should be higher than 3.5 V.
5.4
Power Management
The W78ERD2 provides two modes, idle mode and power-down mode, to reduce power consumption. Both modes are entered by software. The W78ERD2 enters Idle mode when the IDL bit in the PCON register is set. In Idle mode, the internal clock for the processor stops while the internal clock for the peripherals and interrupt logic continues to run. The W78ERD2 leaves Idle mode when an interrupt or a reset occurs. The W78ERD2 enters Power-Down mode when the PD bit in the PCON register is set. In PowerDown mode, all of the clocks are stopped, including the oscillator. The W78ERD2 leaves Power-Down mode when there is a hardware reset or by external interrupts INT0 or INT1, if enabled.
5.5
Reduce EMI Emission
If the crystal frequency is less than 25 MHz, set bit 7 in the option register to 0 to reduce EMI emissions. Please see Option Bits for more information.
5.6
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running, as the W78ERD2 has a special glitch-removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, and all of the other SFR to 00H, with two exceptions--SBUF does not change, and bit 4 in PCON is not cleared.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
6. SPECIAL FUNCTION REGISTER
The following table identifies the Special Function Registers (SFRs) in the W78ERD2, as well as each of their addresses and reset values.
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 Notes: 1. SFRs marked with a plus sign (+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. +B 00000000 +P4 xxxx1111 +ACC 00000000 CCON x0000000 +PSW 00000000 +T2CON 00000000 XICON 00000000 +IP x0000000 +P3 00000000 +IE 00000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 SADDR 00000000 XRAMAH 00000000 SBUF xxxxxxxx P41AL 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 AUXR 00000000 PORT 00000000 PCON 00110000 AUXR1 xxxxx0x0 T2MOD xxxxxx00 XICONH 0xxx0xxx SADEN 00000000 P43AL 00000000 P42AL 00000000 P43AH 00000000 P42AH 00000000 P4CSIN 00000000 WDTRST 00000000 P2EAL 00000000 P2EAH 00000000 RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 SFRFD 00000000 SFRCN 00000000 CHPCON 000xx000 IPH x0000000 CMOD 00xxx000 CCAPM0 x0000000 CCAPM1 x0000000 CCAPM2 x0000000 CCAPM3 x0000000 CCAPM4 x0000000 CKCON xx000xx1 CL 00000000 CCAP0L 00000000 CCAP1L 00000000 CCAP2L 00000000 CCAP3L 00000000 CH 00000000 CCAP0H 00000000 CCAP1H 00000000 CCAP2H 00000000 CCAP3H 00000000 CCAP4H 00000000 CHPENR 00000000 CCAP4L 00000000 FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
The rest of this section explains each SFR, starting with the lowest address.
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W78ERD2/W78ERD2A
Port 0
Bit: 7 P0.7 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0
Mnemonic: P0
Address: 80h
Port 0 is an open-drain, bi-directional I/O port after chip is reset. Besides, it has internal pull-up resisters enabled by setting P0UP of POPT (86H) to high. This port also provides a multiplexed, loworder address/data bus when the W78IRD2 accesses external memory.
Stack Pointer
Bit: 7 SP.7 6 SP.6 5 SP.5 4 SP.4 3 SP.3 2 SP.2 1 SP.1 0 SP.0
Mnemonic: SP
Address: 81h
The Stack Pointer stores the RAM address (scratchpad RAM, not AUX-RAM) where the stack begins. It always points to the top of the stack.
Data Pointer Low
Bit: 7 DPL.7 6 DPL.6 5 DPL.5 4 DPL.4 3 DPL.3 2 DPL.2 1 DPL.1 0 DPL.0
Mnemonic: DPL
Address: 82h
This is the low byte of the standard-8052 16-bit data pointer.
Data Pointer High
Bit: 7 DPH.7 6 DPH.6 5 DPH.5 4 DPH.4 3 DPH.3 2 DPH.2 1 DPH.1 0 DPH.0
Mnemonic: DPH
Address: 83h
This is the high byte of the standard-8052 16-bit data pointer.
Port 4.0 Low-Address Comparator
Bit: 7 6 5 4 3 2 1 0 P40AL.7 P40AL.6 P40AL.5 P40AL.4 P40AL.3 P40AL.2 P40AL.1 P40AL.0 Mnemonic: P40AL Address: 84h
Port 4.0 High-Address Comparator
Bit: 7 6 5 4 3 2 1 0 P40AH.7 P40AH.6 P40AH.5 P40AH.4 P40AH.3 P40AH.2 P40AH.1 P40AH.0 Mnemonic: P40AH Address: 85h
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Port Option Register
Bit: 7 6 5 4 Address: 86h
FUNCTION
3 -
2 -
1 -
0 P0UP
Mnemonic: POPT
BIT NAME
1-7 0
P0UP
Reserve 0: Port 0 pins are open-drain. 1: Port 0 pins are internally pulled-up. Port 0 is structurally the same as Port 2.
Power Control
Bit: 7 6 5 4 POR Address: 87h
FUNCTION
3 GF1
2 GF0
1 PD
0 IDL
SMOD SMOD0 Mnemonic: PCON
BIT NAME
7
SMOD
1: Double the serial-port baud rate in serial port modes 1, 2, and 3. 0: Framing Error Detection Disable. SCON.7 acts as per the standard 8052 function. 1: Framing Error Detection Enable. SCON.7 indicates a Frame Error and acts as the FE (FE_1) flag. Reserved This bit is set to 1 when a power-on reset has occurred. It can be cleared by software. General-purpose flag. General-purpose flag. Set this bit to 1 to go into POWER DOWN mode. Set this bit to 1 to go into IDLE mode.
6
SMOD0
5 4 3 2 1 0
POF GF1 GF0 PD IDL
Timer Control
Bit: 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Mnemonic: TCON
Address: 88h
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W78ERD2/W78ERD2A
BIT
NAME
FUNCTION
7 6 5 4
TF1 TR1 TF0 TR0
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. It can also be set or cleared by software. 1: Turn on Timer 1. 0: Turn off Timer 1. Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. It can also be set or cleared by software. 1: Turn on Timer 0. 0: Turn off Timer 0. Interrupt 1 Edge Detect: This bit is set by the hardware when a falling-edge / lowlevel is detected on INT1 . If INT1 is edge-triggered, this bit is cleared by the hardware when the interrupt service routine begins. Otherwise, it follows the pin. Interrupt 1 type control 1: Interrupt 1 is triggered by a falling-edge on INT1 . 0: Interrupt 1 is triggered by a low-level on INT1 . Interrupt 0 Edge Detect: This bit is set by the hardware when a falling-edge / lowlevel is detected on INT0 . If INT0 is edge-triggered, this bit is cleared by the hardware when the interrupt service routine begins. Otherwise, it follows the pin. Interrupt 0 type control 1: Interrupt 0 is triggered by a falling-edge on INT0 . 0: Interrupt 0 is triggered by a low-level on INT0 .
3
IE1
2
IT1
1
IE0
0
IT0
Timer Mode Control
Bit: 7 GATE 6
C/ T
5 M1
4 M0 Address: 89h
3 GATE
2
C/ T
1 M1
0 M0
Mnemonic: TMOD
BIT NAME
FUNCTION
7
GATE
Gating control: When this bit is set, Timer/Counter 1 is enabled only while the INT1 pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect, and Timer 1 is enabled whenever TR1 is set. Timer or Counter Select: When cleared, Timer 1 is incremented by the internal clock. When set, Timer 1 counts falling edges on the T1 pin. Timer 1 Mode Select bits: See below. Timer 1 Mode Select bits: See below.
6 5 4
C/ T
M1 M0
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Continued
BIT
NAME
FUNCTION
3
GATE
Gating control: When this bit is set, Timer/Counter 0 is enabled only while the INT0 pin is high and the TR0 control bit is set. When cleared, the INT0 pin has no effect, and Timer 0 is enabled whenever TR0 is set. Timer or Counter Select: When cleared, Timer 0 is incremented by the internal clock. When set, Timer 0 counts falling edges on the T0 pin. Timer 0 Mode Select bits: See below. Timer 0 Mode Select bits: See below.
2 1 0
C/ T
M1 M0
M1, M0: Mode Select bits: M1 0 0 1 1 M0 0 1 0 1 Mode Mode 0: 8048 timer, TLx serves as 5-bit pre-scale. Mode 1: 16-bit timer/counter, no pre-scale. Mode 2: 8-bit timer/counter with auto-reload from THx Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer-0 control bits. TH0 is an 8-bit timer only controlled by Timer-1 control bits. (Timer 1) Timer/Counter 1 is stopped.
Timer 0 LSB
Bit: 7 TL0.7 6 TL0.6 5 TL0.5 4 TL0.4 3 TL0.3 2 TL0.2 1 TL0.1 0 TL0.0
Mnemonic: TL0 TL0.7-0: Timer 0 Low byte
Address: 8Ah
Timer 1 LSB
Bit: 7 TL1.7 6 TL1.6 5 TL1.5 4 TL1.4 3 TL1.3 2 TL1.2 1 TL1.1 0 TL1.0
Mnemonic: TL1 TL1.7-0: Timer 1 Low byte
Address: 8Bh
Timer 0 MSB
Bit: 7 TH0.7 6 TH0.6 5 TH0.5 4 TH0.4 3 TH0.3 2 TH0.2 1 TH0.1 0 TH0.0
Mnemonic: TH0 TH0.7-0: Timer 0 High byte
Address: 8Ch
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W78ERD2/W78ERD2A
Timer 1 MSB
Bit: 7 TH1.7 6 TH1.6 5 TH1.5 4 TH1.4 3 TH1.3 2 TH1.2 1 TH1.1 0 TH1.0
Mnemonic: TH1 TH1.7-0: Timer 1 High byte
Address: 8Dh
Auxiliary Register
Bit: 7 6 5 4 Address: 8Eh
FUNCTION
3 -
2 -
1
0
EXTRAM ALEOFF
Mnemonic: AUXR
BIT NAME
7~2 1 0
EXTRAM ALEOFF
Reserve 0 = Enable AUX-RAM 1 = Disable AUX-RAM 0: ALE expression is enabled. 1: ALE expression is disabled.
Port 1
Bit: 7 P1.7 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General-purpose input/output port. Port-read instructions read the port pins, while readmodify-write instructions read the port latch.
Port 4.1 Low Address Comparator
Bit: 7 6 5 4 3 2 1 0
P41AL.7 P41AL.6 P41AL.5 P41AL.4 P41AL.3 P41AL.2 P41AL.1 P41AL.0
Mnemonic: P41AL
Address: 94h
Port 4.1 High Address Comparator
Bit: 7 6 5 4 3 2 1 0
P41AH.7 P41AH.6 P41AH.5 P41AH.4 P41AH.3 P41AH.2 P41AH.1 P41AH.0
Mnemonic: P41AH
Address: 95h
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Serial Port Control
Bit: 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Mnemonic: SCON
BIT NAME
Address: 98h
FUNCTION
7
Serial port, Mode 0 (SM0) bit or Framing-Error (FE) Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. SM0 is described with SM0/FE SMI1 below. When used as FE, this bit indicates whether the stop bit is invalid (FE=1) or valid (FE=0). This bit must be manually cleared by software. Serial port, Mode 1 (SM1) bit: Mode: SM0 SM1 Description Synchronous Asynchronous Asynchronous Asynchronous Length Baud rate 8 10 11 11 6(6T mode)/12(12T mode) Tclk Variable 32/16(6T mode) or 64/32(12T mode) Tclk Variable 0 1 2 3 0 0 1 1 0 1 0 1
6
SM1
Multi-processor communication. 5 SM2 (Modes 2 and 3) Set this bit to enable the multi-processor communication feature. With this feature, RI is not activated if the ninth data bit received (RB8) is 0. (Mode 1) Set this bit to 1 to keep RI de-activated if a valid stop bit is not received. (Mode 0) SM2 controls the serial port clock. If clear, the serial port runs at 1/12 the oscillator. This is compatible with the standard 8052. Receive enable: 4 REN 1 = Serial reception is enabled 0 = Serial reception is disabled 3 TB8 (Modes 2 and 3) This is the ninth bit to be transmitted. This bit is set and cleared by software as desired. (Modes 2 and 3) This is the ninth data bit that was received. 2 RB8 (Mode 1) If SM2 is 0, RB8 is the stop bit that was received. (Mode 0) No function. 1 TI Transmit interrupt flag: This flag is set by the hardware at the end of the eighth bit in mode 0 or at the beginning of the stop bit in modes 1 - 3 during serial transmission. This bit must be cleared by software. Receive interrupt flag: This flag is set by the hardware at the end of the eighth bit in mode 0 or halfway through the stop bit in modes 1 - 3 during serial reception. However, SM2 restricts this bit. This bit can be cleared only by software.
0
RI
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W78ERD2/W78ERD2A
Serial Data Buffer
Bit: 7 6 5 4 3 2 1 0 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Mnemonic: SBUF
BIT NAME
Address: 99h
FUNCTION
7~0
Serial port data is read from or written to this location. It actually consists of two separate, internal 8-bit registers, the receive register and the transmit buffer. Any SBUF read access reads data from the receive register, while write access writes to the transmit buffer.
Port 2
Bit: 7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0
Mnemonic: P2
Address: A0h
Ram High Byte Address
Bit: 7 0 6 0 5 0 4 0 3 0 2 0 1 0
XRAMAH.1 XRAMAH.0
Mnemonic: XRAMAH The AUX-RAM high byte address
Address: A1h
Auxiliary 1 Register
Bit: 7 6 5 4 3 GF2 2 0 1 0 DPS
Mnemonic: AUXR1
BIT NAME
Address: A2h
FUNCTION
7~4 3 2 1 0
GF2 0 DPS
Reserved General purpose, user-defined flag. The bit cannot be written and is always read as 0. Reserved 0 = switch to DPTR0 1 = switch to DPTR1
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Watchdog Timer Reset Register
Bit: 7 6 5 4 3 2 1 0
WDTRST.7 WDTRST.6 WDTRST.5 WDTRST.4 WDTRST.3 WDTRST.2 WDTRST.1 WDTRST.0
Mnemonic: WDTRST
Address: A6h
Interrupt Enable
Bit: 7 EA Mnemonic: IE
BIT NAME
6 EC
5 ET2
4 ES
3 ET1
2 EX1
1 ET0
0 EX0
Address: A8h
FUNCTION
7 6 5 4 3 2 1 0
EA EC ET2 ES ET1 EX1 ET0 EX0
Global interrupt enable. Enable/disable all interrupts except for PFI. Enable PCA interrupt. Enable Timer 2 interrupt. Enable Serial port interrupt. Enable Timer 1 interrupt. Enable external interrupt INT1. Enable Timer 0 interrupt. Enable external interrupt INT0 .
SLAVE ADDRESS
Bit: 7 6 5 4 3 2 1 0
Mnemonic: SADDR
BIT NAME
Address: A9h
FUNCTION
7~0
SADDR
The SADDR should be programmed to the given or broadcast address for serial port to which the slave processor is designated.
Port 4.2 Low Address Comparator
Bit: 7 6 5 4 3 2 1 0
P42AL.7 P42AL.6 P42AL.5 P42AL.4 P42AL.3 P42AL.2 P42AL.1 P42AL.0
Mnemonic: P42AL
Address: Ach
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W78ERD2/W78ERD2A
Port 4.2 High Address Comparator
Bit: 7 6 5 4 3 2 1 0
P42AH.7 P42AH.6 P42AH.5 P42AH.4 P42AH.3 P42AH.2 P42AH.1 P42AH.0
Mnemonic: P42AH
Address: ADh 5 4 3 2 1 0
Port 4 CS Sign
Bit: 7 6
P4CSIN.7 P4CSIN.6 P4CSIN.5 P4CSIN.4 P4CSIN.3 P4CSIN.2 P4CSIN.1 P4CSIN.0
Mnemonic: P4CSIN
Address: AEh 5 P3.5 4 P32.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0
Port 3
Bit: 7 P3.7 6 P32.6
Mnemonic: P3 Bit: 7 6
Address: B0h 5 4 3 2 1 0
Port 4.3 Low Address Comparator
P43AL.7 P43AL.6 P43AL.5 P43AL.4 P43AL.3 P43AL.2 P43AL.1 P43AL.0
Mnemonic: P43AL Bit: 7 6 5
Address: B4h 4 3 2 1 0
Port 4.3 High Address Comparator
P43AH.7 P43AH.6 P43AH.5 P43AH.4 P43AH.3 P43AH.2 P43AH.1 P43AH.0
Mnemonic: P43AH
Address: B5h 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
Interrupt Priority High
Bit: 7 6 PPCH
Mnemonic: IPH
BIT NAME
Address: B8h
FUNCTION
7 6 5 4 3 2 1 0
PPCH PT2H PSH PT1H PX1H PT0H PX0H
This bit is not implemented and is always read high. 1: Set the priority of the PCA interrupt to the highest level. 1: Set the priority of the Timer 2 interrupt to the highest level. 1: Set the priority of the Serial Port interrupt to the highest level. 1: Set the priority of the Timer 1 interrupt to the highest level. 1: Set the priority of external interrupt INT1 to the highest level. 1: Set the priority of the Timer 0 interrupt to the highest level. 1: Set the priority of external interrupt INT0 to the highest level. Publication Release Date: February 14, 2007 Revision A10
- 17 -
W78ERD2/W78ERD2A
Interrupt Priority
Bit: 7 6 PPC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Mnemonic: IP
BIT NAME
Address: B8h
FUNCTION
7 6 5 4 3 2 1 0
PPC PT2 PS PT1 PX1 PT0 PX0
This bit is not implemented and is always read high. 1: Set the priority of the PCA interrupt one level higher. 1: Set the priority of the Timer 2 interrupt one level higher. 1: Set the priority of the Serial Port interrupt one level higher. 1: Set the priority of the Timer 1 interrupt one level higher. 1: Set the priority of external interrupt INT1 one level higher. 1: Set the priority of the Timer 0 interrupt one level higher. 1: Set the priority of external interrupt INT0 one level higher.
Slave Address Mask Enable
Bit: 7 6 5 4 3 2 1 0
Mnemonic: SADEN
BIT NAME
Address: B9h
FUNCTION
7~0
This register enables the Automatic Address Recognition feature of the serial port. When a bit in SADEN is set to 1, the same bit in SADDR is compared to the SADEN incoming serial data. When a bit in SADEN is set to 0, the same bit in SADDR is a "don't care" value in the comparison. The serial port interrupt occurs only if all the SADDR bits where SADEN is set to 1 match the incoming serial data.
On-Chip Programming Control
Bit: 7
SWRST/ REBOOT
6
-
5
-
4
-
3
-
2
0
1
0
FBOOTSL FPROGEN
Mnemonic: CHPCON
Address: BFh
- 18 -
W78ERD2/W78ERD2A
BIT
NAME
FUNCTION
7 6-2
W: SWRESET R: REBOOT -
1
FBOOTSL
0
FPROGEN
When FBOOTSL and FPROGEN are set to 1, set this bit to 1 to force the microcontroller to reset to the initial condition, just like power-on reset. This action re-boots the microcontroller and starts normal operation. Read this bit to determine whether or not a hardware reboot is in progress. Reserved Program Location Selection. This bit should be set before entering ISP mode. 0: The Loader Program is in the 64-KB AP Flash EPROM. The 4-KB LD Flash EPROM is the destination for re-programming. 1: The Loader Program is in the 4-KB memory bank. The 64-KB AP Flash EPROM is the destination for re-programming. FLASH EPROM Programming Enable. 1: Enable in-system programming mode. In this mode, erase, program and read operations are achieved during device enters idle state. 0: Disable in-system programming mode. The on-chip flash memory is read-only.
CHPCON has an unrestricted read access, however, the write access is protected by timed-access protection. See the section of timed-access protection for more information.
External Interrupt Control
Bit: 7 PX3 6 EX3 5 IE3 4 IT3 3 PX2 2 EX2 1 IE2 0 IT2
Mnemonic: XICON
BIT NAME
Address: C0h
FUNCTION
7 6 5 4 3 2 1 0
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
1: Set the priority of external interrupt INT3 one level higher. 1: Enable external interrupt INT3 . Interrupt INT3 flag. This bit is set and cleared automatically by the hardware when the interrupt is detected and processed. 1: INT3 is falling-edge triggered 0: INT3 is low-level triggered 1: Set the priority of external interrupt INT2 one level higher. 1: Enable external interrupt INT2 . Interrupt INT2 flag. This bit is set and cleared automatically by the hardware when the interrupt is detected and processed. 1: INT2 is falling-edge triggered 0: INT2 is low-level triggered
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
External Interrupt High Control
Bit: 7 PXH3 6 5 4 3 PXH2 2 1 0 -
Mnemonic: XICON
BIT NAME
Address: C1h
FUNCTION
7 6-4 3 2-0
PXH3 PXH2 -
1: Set the priority of external interrupt INT3 to the highest level. Reserved 1: Set the priority of external interrupt INT2 to the highest level. Reserved
Port 4 Control Register A
Bit: 7 6 5 4 3 2 1 0
P41FUN1 P41FUN0 P41CMP1 P41CMP0 P40FUN1 P40FUN0 P40CMP1 P40CMP0
Mnemonic: P4CONA
BIT NAME
Address: C2h
FUNCTION
7, 6 5, 4 3, 2 1, 0
P41FUN1 P41FUN0 P41CMP1 P41CMP0 P40FUN1 P40FUN0 P40CMP1 P40CMP0
P4.1 function control bits, similar to P43FUN1 and P43FUN0 below. P4.1 address-comparator length control bits, similar to P43CMP1 and P43CMP0 below. P4.0 function control bits, similar to P43FUN1 and P43FUN0 below. P4.0 address-comparator length control bits, similar to P43CMP1 and P43CMP0 below.
Port 4 Control Register B
Bit: 7 6 5 4 3 2 1 0
P43FUN1 P43FUN0 P43CMP1 P43CMP0 P42FUN1 P42FUN0 P42CMP1 P42CMP0
Mnemonic: P4CONB
Address: C3h
- 20 -
W78ERD2/W78ERD2A
BIT
NAME
FUNCTION
7, 6
P43FUN1 P43FUN0
5, 4
P43CMP1 P43CMP0 P42FUN1 P42FUN0 P42CMP1 P42CMP0
00: Mode 0. P4.3 is a general purpose I/O port, like Port 1. 01: Mode 1. P4.3 is a read-strobe signal for chip-select purposes. address range depends on SFR P43AH, P43AL, P43CMP1 P43CMP0. 10: Mode 2. P4.3 is a write-strobe signal for chip-select purposes. address range depends on SFR P43AH, P43AL, P43CMP1 P43CMP0. 11: Mode 3. P4.3 is a read/write-strobe signal for chip-select purposes. address range depends on SFR P43AH, P43AL, P43CMP1, P43CMP0. Chip-select signal address comparison: 00: Compare the full 16-bit address with P43AH and P43AL. 01: Compare the 15 MSB of the 16-bit address with P43AH and P43AL. 10: Compare the 14 MSB of the 16-bit address with P43AH and P43AL. 11: Compare the 8 MSB of the 16-bit address with P43AH. P4.2 function control bits, similar to P43FUN1 and P43FUN0 above. P4.2 address-comparator length control bits, similar to P43CMP1 and P43CMP0 above.
The and The and The and
3, 2 1, 0
F/W Flash Low Address
Bit: 7 6 5 4 3 2 1 0
Mnemonic: SFRAL F/W flash low byte address
Address: C4h
F/W Flash High Address
Bit: 7 6 5 4 3 2 1 0
Mnemonic: SFRAH F/W flash high byte address
Address: C5h
F/W Flash Data
Bit: 7 6 5 4 3 2 1 0
Mnemonic: SFRFD F/W flash data
Address: C6h
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
F/W Flash Control
Bit: 7 0 6 WFWIN 5 OEN 4 CEN 3 CTRL3 2 CTRL2 1 CTRL1 0 CTRL0
Mnemonic: SFRCN
BIT NAME
Address: C7h
FUNCTION
7
-
Reserved On-chip Flash EPROM bank select for in-system programming. This bit should be defined by the loader program in ISP mode. 0: 64-KB Flash EPROM is the destination for re-programming. 1: 4-KB Flash EPROM is the destination for re-programming. Flash EPROM output enable. Flash EPROM chip enable.
6
WFWIN
5 4 3-0
OEN CEN
CTRL[3:0] Flash control signals
Timer 2 Control
Bit: 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2
Mnemonic: T2CON
BIT NAME
Address: C8h
FUNCTION
7
TF2
Timer 2 overflow flag: If RCLK and TCLK are 0, this bit is set when Timer 2 overflows or when the count is equal to the value in the capture register in down-count mode. This bit can also be set by software, and it can only be cleared by software. Timer 2 External Flag: When Timer 2 is in either capture or auto-reload mode and DCEN is 0, a negative transition on the T2EX pin (P1.1) and EXEN2=1 sets this flag. This flag can also be set by software. Once set, this flag generates a Timer-2 interrupt, if enabled, and it must be cleared by software. Receive Clock Flag: Set this bit to force Timer 2 into baud-rate generator mode when receiving data on the serial port in modes 1 or 3. 1 = Timer 2 overflow is the time base. 0 = Timer 1 overflow is the time base. Transmit clock Flag: Set this bit to force Timer 2 into baud-rate generator mode when transmitting data on the serial port in modes 1 or 3. 1 = Timer 2 overflow is the time base. 0 = Timer 1 overflow is the time base.
6
EXF2
5
RCLK
4
TCLK
- 22 -
W78ERD2/W78ERD2A
Continued
BIT
NAME
FUNCTION
3
Timer 2 External Enable: If Timer 2 is not in baud-rate generator mode (see RCLK EXEN2 and TCLK above), set this bit to allow a negative transition on the T2EX pin to capture/reload Timer 2 counter. Timer 2 Run Control: TR2 1 = Enable Timer 2. 0 = Disable Timer 2, which preserves the current value in TH2 and TL2. Counter/Timer select:
2
1
C/T2
0 = Timer 2 operates as a timer at a speed controlled by T2M (CKCON.5) 1 = Timer 2 counts negative edges on the T2EX pin. Capture/Reload Select: If EXEN2 is set to 1, this bit determines whether the capture or auto-reload function is activated.
0
CP/RL2
0 = auto-reload when timer 2 overflows or a falling edge is detected on T2EX 1 = capture each falling edge is detected on T2EX If either RCLK or TCLK is set, this bit has no function, as Timer 2 runs in autoreload mode.
Timer 2 Mode
Bit: 7 6 5 4 3 2 1 T2OE 0 DCEN
Mnemonic: T2MOD
BIT NAME
Address: C9h
FUNCTION
7~2 1 0
T2OE DCEN
Reserved Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. Down Count Enable: Setting DCEN to 1 allows T2EX pin to control the direction that Timer 2 counts in 16-bit auto-reload mode.
Timer 2 Capture Low
Bit: 7 6 5 4 3 2 1 0
RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
Mnemonic: RCAP2L
Address: CAh
RCAP2L Timer 2 Capture LSB: In capture mode, RCAP2L is used to capture the TL2 value. In autoreload mode, RCAP2L is used as the LSB of the 16-bit reload value.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Timer 2 Capture High
Bit: 7 6 5 4 Address: CBh 3 2 1 0
RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
Mnemonic: RCAP2H
RCAP2H Timer 2 Capture HSB: In capture mode, RCAP2H is used to capture the TH2 value. In autoreload mode, RCAP2H is used as the MSB of the 16-bit reload value.
Timer 2 Register Low
Bit: 7
TL2.7
6
TL2.6
5
TLH2.5
4
TL2.4
3
TL2.3
2
TL2.2
1
TL2.1
0
TL2.0
Mnemonic: TL2 TL2 Timer 2 LSB
Address: CCh
Timer 2 Register High
Bit: 7
TH2.7
6
TH2.6
5
TH2.5
4
TH2.4
3
TH2.3
2
TH2.2
1
TH2.1
0
TH2.0
Mnemonic: TH2 TL2 Timer 2 MSB
Address: CDh
Program Status Word
Bit: 7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
F1
0
P
Mnemonic: PSW
BIT NAME
Address: D0h
FUNCTION
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV F1 P
Carry flag: Set when an arithmetic operation results in a carry being generated from the ALU. It is also used as the accumulator for bit operations. Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble. General-purpose, user-defined flag 0. Register bank select bits: See below. Register bank select bits: See below. Overflow flag: Set when a carry was generated from the seventh bit but not from the eighth bit as a result of the previous operation, or vice-versa. General-purpose, user-defined flag 1. Parity flag: Set and cleared by the hardware to indicate an odd or even number, respectively, of 1's in the accumulator.
- 24 -
W78ERD2/W78ERD2A
RS.1-0: Register bank select bits:
RS1 RS0 REGISTER BANK ADDRESS
0 0 1 1
0 1 0 1
0 1 2 3
00-07h 08-0Fh 10-17h 18-1Fh
PCA Counter Control Register
Bit: 7 CF 6 CR 5 4 CCF4 Address: D8h 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Mnemonic: CCON
PCA Counter Mode Register
Bit: 7 CIDL 6 WDTE 5 4 Address: D9h 3 2 CPS1 1 CPS0 0 ECF
Mnemonic: CMOD
PCA Module 0 Register
Bit: 7 6 5 4 Address: DAh 3 MAT0 2 TOG0 1 PWM0 0 ECCF0 ECOM0 CAPP0 CAPN0
Mnemonic: CCAPM0
PCA Module 1 Register
Bit: 7 6 5 4 Address: DBh 3 MAT1 2 TOG1 1 PWM1 0 ECCF1 ECOM1 CAPP1 CAPN1
Mnemonic: CCAPM1
PCA Module 2 Register
Bit: 7 6 5 4 Address: DCh 3 MAT2 2 TOG2 1 PWM2 0 ECCF2 ECOM2 CAPP2 CAPN2
Mnemonic: CCAPM2
PCA Module 3 Register
Bit: 7 6 5 4 Address: DDh 3 MAT3 2 TOG3 1 PWM3 0 ECCF3 ECOM3 CAPP3 CAPN3
Mnemonic: CCAPM3
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
PCA Module 4 Register
Bit: 7 6 5 4 Address: DEh 3 MAT4 2 TOG4 1 PWM4 0 ECCF4 ECOM4 CAPP4 CAPN4
Mnemonic: CCAPM4
Clock Control Register
Bit: 7 6 5 T2M 4 T1M Address: DFh
FUNCTION
3 T0M
2 -
1 -
0 MD
Mnemonic: CKCON
BIT NAME
7 6
-
Reserved Reserved Timer 2 clock select: 0 = Divide-by-6 clock 1 = Divide-by-12 clock This bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. Timer 1 clock select: 0 = Divide-by-6 clock 1 = Divide-by-12 clock This bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. Timer 0 clock select: 0 = Divide-by-6 clock 1 = Divide-by-12 clock This bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. Reserved Reserved Stretch MOVX select bits: This bit is used to select the stretch value for the MOVX instruction, which enables the microcontroller to access slower memory devices or peripherals transparently and without the need for external circuits. The RD or WR strobe and all internal timings are stretched by the selected interval. The default value is 1 cycle. For faster access, set the value to 0.
5
T2M
4
T1M
3
T0M
2 1
-
0
MD
CKCON has an unrestricted read access, however, the write access is protected by timed-access protection. See the section of timed-access protection for more information.
- 26 -
W78ERD2/W78ERD2A
Accumulator
Bit: 7 ACC.7 6 ACC.6 5 ACC.5 4 ACC.4 Address: E0h 3 ACC.3 2 ACC.2 1 ACC.1 0 ACC.0
Mnemonic: ACC
ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.
Port 4
Bit: 7
-
6
-
5
-
4
-
3
2
1
P4.1
0
P4.0
P4.3/INT2 P4.2/INT3
Mnemonic: ACC
Address: E8h
P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups.
BIT NAME FUNCTION
7-4 3 2 1 0
P4.3 P4.2 P4.1 P4.0
Reserved Port 4 Data bit which outputs to pin P4.3 in mode 0, or external interrupt INT2 . Port 4 Data bit which outputs to pin P4.2 in mode 0, or external interrupt INT3 . Port 4 Data bit which outputs to pin P4.1 in mode 0. Port 4 Data bit which outputs to pin P4.0 in mode 0.
PCA Counter Low Register
Bit: 7 CL.7 6 CL.6 5 CL.6 4 CL.4 3 CL.3 2 CL.2 1 CL.1 0 CL.0
Mnemonic: CL
Address: E9h
PCA Module 0 Compare/Capture Low Register
Bit: 7 6 5 4 3 2 1 0
CCAP0L.7 CCAP0L.6 CCAP0L.5 CCAP0L.4 CCAP0L.3 CCAP0L.2 CCAP0L.1 CCAP0L.0
Mnemonic: CCAP0L
Address: EAh
PCA Module 1 Compare/Capture Low Register
Bit: 7 6 5 4 3 2 1 0
CCAP1L.7 CCAP1L.6 CCAP1L.5 CCAP1L.4 CCAP1L.3 CCAP1L.2 CCAP1L.1 CCAP1L.0
Mnemonic: CCAP1L
Address: EBh
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
PCA Module 2 Compare/Capture Low Register
Bit: 7 6 5 4 3 2 1 0
CCAP2L.7 CCAP2L.6 CCAP2L.5 CCAP2L.4 CCAP2L.3 CCAP2L.2 CCAP2L.1 CCAP2L.0
Mnemonic: CCAP2L
Address: ECh
PCA Module 3 Compare/Capture Low Register
Bit: 7 6 5 4 3 2 1 0
CCAP3L.7 CCAP3L.6 CCAP3L.5 CCAP3L.4 CCAP3L.3 CCAP3L.2 CCAP3L.1 CCAP3L.0
Mnemonic: CCAP3L
Address: EDh
PCA Module 4 Compare/Capture Low Register
Bit: 7 6 5 4 3 2 1 0
CCAP4L.7 CCAP4L.6 CCAP4L.5 CCAP4L.4 CCAP4L.3 CCAP4L.2 CCAP4L.1 CCAP4L.0
Mnemonic: CCAP4L
Address: EEh
B Register
Bit: 7
B.7
6
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
0
B.0
Mnemonic: B
Address: F0h
B.7-0: The B register is the standard 8052 register that serves as a second accumulator.
Chip Enable Register
Bit: 7 6 5 4 3 2 1 0
Mnemonic: CHPENR
Address: F6h
PCA Counter High Register
Bit: 7
CH.7
6
CH.6
5
CH.6
4
CH.4
3
CH.3
2
CH.2
1
CH.1
0
CH.0
Mnemonic: CH
Address: F9h
PCA Module 0 Compare/Capture High Register
Bit: 7 6 5 4 3 2 1 0
CCAP0H.7CCAP0H.6 CCAP0H.5CCAP0H.4CCAP0H.3CCAP0H.2CCAP0H.1 CCAP0H.0
Mnemonic: CCAP0H
Address: FAh
- 28 -
W78ERD2/W78ERD2A
PCA Module 1 Compare/Capture High Register
Bit: 7 6 5 4 3 2 1 0
CCAP1H.7CCAP1H.6 CCAP1H.5CCAP1H.4CCAP1H.3CCAP1H.2CCAP1H.1 CCAP1H.0
Mnemonic: CCAP1H
Address: FBh
PCA Module 2 Compare/Capture High Register
Bit: 7 6 5 4 3 2 1 0
CCAP2H.7CCAP2H.6 CCAP2H.5CCAP2H.4CCAP2H.3CCAP2H.2CCAP2H.1 CCAP2H.0
Mnemonic: CCAP2H
Address: FCh
PCA Module 3 Compare/Capture High Register
Bit: 7 6 5 4 3 2 1 0
CCAP3H.7CCAP3H.6 CCAP3H.5CCAP3H.4CCAP3H.3CCAP3H.2CCAP3H.1 CCAP3H.0
Mnemonic: CCAP3H
Address: FDh
PCA Module 4 Compare/Capture High Register
Bit: 7 6 5 4 3 2 1 0
CCAP4H.7 CCAP4H.6 CCAP4H.5 CCAP4H.4 CCAP4H.3 CCAP4H.2 CCAP4H.1 CCAP4H.0
Mnemonic: CCAP4H
Address: FEh
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
7. PORT 4 AND BASE ADDRESS REGISTERS
Port 4, address E8H, is a 4-bit, multi-purpose, programmable I/O port. Each bit can be configured individually, and registers P4CONA and P4CONB contain the control bits that select the mode of each pin. Each pin has four operating modes. Mode 0: Bi-directional I/O port, like port 1. P4.2 and P4.3 serve as external interrupts INT3 and INT2 , if enabled. Mode 1: Read-strobe signals synchronized with the RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: Write-strobe signals synchronized with the WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: Read/write-strobe signals synchronized with the RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. In modes 1 - 3, the address range for chip-select signals depends on the contents of registers P4xAH and P4xAL, which contain the high-order byte and low-order byte, respectively, of the 16-bit address comparator for P4.x. This is illustrated in the following schematic.
P4 REGISTER P4.x
P4xCSINV DATA I/O RD_CS MUX 4->1 WR_CS
READ WRITE
RD/WR_CS PIN P4.x
ADDRESS BUS EQUAL REGISTER P4xAL P4xAH
P4xFUN0 P4xFUN1
Bit Length Selectable comparator REGISTER P4xCMP0 P4xCMP1
P4.x INPUT DATA BUS
Figure 7-1 For example, the following program sets up P4.0 as a write-strobe signal for I/O port addresses 1234H - 1237H with positive polarity, while P4.1 - P4.3 are used as general I/O ports.
- 30 -
W78ERD2/W78ERD2A
MOV P40AH, #12H MOV P40AL, #34H MOV P4CONA, #00001010B MOV P4CONB, #00H MOV P2ECON, #10H ; Base I/O address 1234H for P4.0 ; P4.0 is a write-strobe signal; address lines A0 and A1 are masked. ; P4.1 - P4.3 are general I/O ports ; Set P40SINV to 1 to invert the P4.0 write-strobe to positive polarity.
Then, any instruction MOVX @DPTR, A (where DPTR is in 1234H - 1237H) generates a positivepolarity, write-strobe signal on pin P4.0, while the instruction MOV P4, #XX puts bits 3 - 1 of data #XX on pins P4.3 - P4.1.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
8. INTERRUPTS
This section provides more information about external interrupts INT2 and INT3 and provides an overview of interrupt priority levels and polling sequences.
8.1
External Interrupts 2 and 3
The W78ERD2 offers two additional external interrupts, INT2 and INT3 , similar to external interrupts INT0 and INT1 in the standard 80C52. These interrupts are configured by the XICON (External Interrupt Control) register, which is not a standard register in the 80C52. Its address is 0C0H. XICON is bit-addressable; for example, "SETB 0C2H" sets the EX2 bit of XICON.
8.2
Interrupt Priority
Each interrupt has one of four priority levels in the W78ERD2, as shown below.
Four-level interrupt priority
PRIORITY BITS
IPH.X
IP.X
INTERRUPT PRIORITY LEVEL
0 0 1 1
0 1 0 1
Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority)
Interrupts with the same priority level are polled in the sequence indicated below.
Nine-source interrupt information
INTERRUPT SOURCE POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL VECTOR ADDRESS
External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Programmable Counter Array Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3
0 (highest) 1 2 3 4 5 6 7 8 (lowest)
IE.0 IE.1 IE.2 IE.3 IE.6 IE.4 IE.5 XICON.2 XICON.6
TCON.0 TCON.2 XICON.0 XICON.3
03H 0BH 13H 1BH 33H 23H 2BH 3BH 43H
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W78ERD2/W78ERD2A
9. PROGRAMMABLE TIMERS/COUNTERS
The W78ERD2 has three 16-bit programmable timer/counters.
Time-Base Selection
The W78ERD2 offers two speeds for the timer. The timers can count at 1/12 of the clock, the same speed they have in the standard 8051 family. Alternatively, the timers can count at 1/6 of the clock, called turbo mode. The speed is controlled by bits T0M, T1M and T2M bits in CKCON. The default value is zero, which selects 1/12 of the clock. These 3 bits, T0M, T1M and T2M, have no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle.
9.1
Timer 0 and Timer 1
Timers 0 and 1 each have a 16-bit timer/counter which consists of two eight-bit registers: Timer 0 consists of TH0 (8 MSB) and TL0 (8 LSB), and Timer 1 consists of TH1 and TL1. These timers/counters can be configured to operate either as timers, machine-cycle counters or counters based on external inputs. The "Timer" or "Counter" function itself is selected by the corresponding " C/ T " bit in the TMOD register: bit 2 for Timer 0 and bit 6 for Timer 1. In addition, each timer/counter can operate in one of four possible modes, which are selected by bits M0 and M1 in TMOD. The rest of this section explains the time-base for the timers and then introduces each mode.
Mode 0
In mode 0, the timer/counter is a 13-bit counter whose eight MSB are in THx and five LSB are the five lower bits in TLx. The upper three bits in TLx are ignored. Because THx and TLx are read separately, the timer/counter acts like an eight-bit counter with a five-bit, divide-by-32 pre-scale. Counting is enabled only when TRx is set and either GATE = 0 or INTx = 1. What the timer/counter counts depends on C/ T . When C/ T is set to 0, the timer/counter counts the negative edges of the clock according to the time-base selected by bits TxM in CKCON. When C/ T is set to 1, it counts falling edges on T0 (P3.4, for Timer 0) or T1 (P3.5, for Timer 1). When the 13-bit counter reaches 1FFFh, the next count rolls over the timer/counter to 0000h, and the timer overflow flag TFx (in TCON) is set. If enabled, an interrupt occurs.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
T0M = CKCON.3 (T1M = CKCON.4) 1/6 1 0 C/T = TMOD.2 (C/T = TMOD.6) 0 1 T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) 0
Timer 1 functions are shown in brackets
M1,M0 = TMOD.1,TMOD.0 (M1,M0 = TMOD.5,TMOD.4) 00 4 TL0 (TL1) 7 01 0 TH0 (TH1) 7
osc
1/12
GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
TFx TF0 (TF1)
Interrupt
Figure 9-1 Timer/Counter Mode 0 & Mode 1
Mode 1
Mode 1 is similar to mode 0, except that the timer/counter is 16-bit counter, not a 13-bit counter. All the bits in THx and TLx are used. Roll-over occurs when the timer moves from FFFFh to 0000h.
Mode 2
Mode 2 is similar to mode 0, except that TLx acts like an eight-bit counter and THx holds the autoreload value for TLx. When the TLx register overflows from FFh to 00h, the timer overflow flag TFx bit (in TCON) is set, TLx is reloaded with the contents of THx, and the counting process continues. The reload operation does not affect the THx register.
T0M = CKCON.3 (T1M = CKCON.4) 1/6
Timer 1 functions are shown in brackets
TL0 (TL1)
osc
1/12 T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
1 0
C/T = TMOD.2 (C/T = TMOD.6) 0 1
0
7
TFx
TF0 (TF1)
Interrupt
0
TH0 (TH1)
7
Figure 9-2 Timer/Counter Mode 2
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W78ERD2/W78ERD2A
Mode 3
Mode 3 is used when an extra eight-bit timer is needed, and it has different effects on Timer 0 and Timer 1. Timer 0 separates TL0 and TH0 into two separate eight-bit count registers. TL0 uses the Timer 0 control bits C/ T , GATE, TR0, INT0 and TF0 and can count clock cycles (clock / 12 or clock / 6) or falling edges on pin T0. Meanwhile, TH0 takes over TR1 and TF1 from Timer 1 and can count clock cycles (clock / 12 or clock / 6). Mode 3 simply freezes Timer 1, which provides a way to turn it on and off. When Timer 0 is in mode 3, Timer 1 can still be used in modes 0, 1 and 2, but its flexibility is limited. Timer 1 can still be used as a timer / counter (or a baud-rate generator for the serial port) and retains the use of GATE and INT1 pin, but it no longer has control over the overflow flag TF1 and enable bit TR1.
T0M = CKCON.3 1 C/T = TMOD.2 0 0 1
1/6
osc
1/12 T0 = P3.4 TR0 = TCON.4 GATE = TMOD.3 INT0 = P3.2
TL0
0
7
TF0
Interrupt
TH0 TR1 = TCON.6
0
7
TF1
Interrupt
Figure 9-3 Timer/Counter 0 Mode 3
9.2
Timer/Counter 2
Timer 2 is a 16-bit up/down counter equipped with a capture/reload capability. It is configured by the T2MOD register and controlled by the T2CON register. As with Timers 0 and 1, Timer 2 can count clock cycles (fosc / 12 or fosc / 6) or the external T2 pin, as selected by C/ T2 , and there are four operating modes, each discussed below.
Capture Mode
Capture mode is enabled by setting the CP/RL2 bit in the T2CON register. In capture mode, Timer 2 serves as a 16-bit up-counter. When the counter rolls over from FFFFh to 0000h, the TF2 bit is set, and, if enabled, an interrupt is generated. If the EXEN2 bit is set, then a negative transition on the T2EX pin captures the value in TL2 and TH2 registers in the RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which may also generate an interrupt.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
RCLK+TCLK=0, CP/RL2 =T2CON.0=1
1/6 T2M = CKCON.5 1 0 0 1 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1 C/T2 = T2CON.1 TL2 TH2 T2CON.7 TF2
osc
1/12
Timer 2 Interrupt
RCAP2L RCAP2H
EXEN2 = T2CON.3
EXF2 T2CON.6
Figure 9-4 16-Bit Capture Mode
Auto-reload Mode, Counting up
This mode is enabled by clearing the CP/RL2 bit in T2CON and the DCEN bit in T2MOD. In this mode, Timer 2 is a 16-bit up-counter. When the counter rolls over from FFFFh to 0000h, the contents of RCAP2L and RCAP2H are automatically reloaded into TL2 and TH2, and the timer overflow bit TF2 is set. If the EXEN2 bit is set, then a negative transition of T2EX pin also causes a reload, which also sets the EXF2 bit in T2CON. RCLK+TCLK=0, CP/RL2 =T2CON.0=0, DCEN=0
1/6
osc 1/12 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1
RCAP2L RCAP2 H
T2M = CKCON.5
1
0
C/T2 = T2CON.1 0
T2CON.7 TL2 TH2
1
TF2
Timer 2 Interrupt
EXEN2 = T2CON.3
EXF2 T2CON.6
Figure 9-5 16-Bit Auto-reload Mode, Counting Up
Auto-reload Mode, Counting Up/Down
This mode is enabled when the CP/RL2 bit in T2CON is clear and the DCEN bit in T2MOD is set. In this mode, Timer 2 is an up/down-counter whose direction is controlled by the T2EX pin (1 = up, 0 = down). When Timer 2 overflows while counting up, the counter is reloaded by RCAP2L and RCAP2H. When Timer 2 is counting down, the counter is reloaded with FFFFh when Timer 2 is equal to RCAP2L and RCAP2H. In either case, the timer overflow bit TF2 is set, and the EXF2 bit is toggled, though EXF2 can not generate an interrupt in this mode.
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W78ERD2/W78ERD2A
RCLK+TCLK=0, CP/RL2 =T2CON.0=0, DCEN=1
Down Counting Reload Value
0FFh 1/6 T2M = CKCON.5
0FFh
osc
1/12 T2 = P1.0 TR2 = T2CON.2
1 0
C/T = T2CON.1 0
T2CON.7
TL2 TH2
1
TF2
Timer 2 Interrupt
RCAP2L
RCAP2H
T2EX = P1.1
Up Counting Reload Value
EXF2 T2CON.6
Figure 9-6 16-Bit Auto-reload Up/Down Counter
Baud Rate Generator Mode
Baud-rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register. In baud-rate generator mode, Timer 2 is a 16-bit up-counter that automatically reloads when it overflows, but this overflow does not set the timer overflow bit TF2. If EXEN2 is set, then a negative transition on the T2EX pin sets EXF2 bit in T2CON and, if enabled, generates an interrupt request. RCLK+TCLK=1
osc
T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1
0
C/T = T2CON.1 TL2 TH2
1
Timer 2 overflow
RCAP2LRCAP2H
EXEN2 = T2CON.3
EXF2 T2CON.6
Figure 9-7 Baud Rate Generator Mode
Timer 2 Interrupt
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
10. ENHANCED FULL DUPLEX SERIAL PORT
The W78ERD2 serial port is a full-duplex port, and the W78ERD2 provides additional features such as frame-error detection and automatic address recognition. The serial port runs in one of four operating modes.
Serial Ports Modes
SM1 SM0 MODE TYPE BAUD CLOCK FRAME SIZE START BIT STOP BIT 9TH BIT FUNCTION
0 0 1 1
0 1 0 1
0 1 2 3
Synch. Asynch. Asynch. Asynch.
12 TCLKS Timer 1 or 2 32 or 64 TCLKS Timer 1 or 2
8 bits 10 bits 11 bits 11 bits
No 1 1 1
No 1 1 1
None None 0, 1 0, 1
In synchronous mode (mode 0), the W78ERD2 generates the clock and operates in a half-duplex mode. In asynchronous modes (modes 1 - 3), full-duplex operation is available so that the serial port can simultaneously transmit and receive data. In any mode, register SBUF functions as both the transmit register and the receive buffer. Any write to SBUF writes to the transmit register, while any read from SBUF reads from the receive buffer. The rest of this section discusses each operating mode and then discusses frame-error detection and automatic address recognition.
10.1 MODE 0
Mode 0 is a half-duplex, synchronous mode. RxD transmits and receives serial data, and TxD transmits the shift clock. The TxD clock is provided by the W78ERD2. Eight bits are transmitted or received per frame, LSB first. The baud rate is fixed at 1/12 of the oscillator frequency. The functional block diagram is shown below.
osc
Write to SBUF
TX START TX CLOCK
Internal Data Bus
PARIN LOAD CLOCK
SOUT
RXD P3.0 Alternate Output Function
12
TX SHIFT TI RI
Transmit Shift Register Serial Port Interrupt TXD P3.1 Alternate Output function Read SBUF SBUF Internal Data Bus
SERIAL CONTROLLE
RX CLOCK
SHIFT CLOCK LOAD SBUF RX SHIFT CLOCK PAROUT SIN
RI REN RXD P3.0 Alternate Iutput function
RX START
SBUF
Receive Shift Register
Figure 10-1 Serial Port Mode 0
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W78ERD2/W78ERD2A
As mentioned before, data enters and leaves the serial port on RxD. TxD line provides the shift clock, which shifts data into and out of the W78ERD2 and the device at the other end of the line. Any instruction that writes to SBUF starts the transmission. The shift clock is activated, and the data is shifted out on the RxD pin until all eight bits are transmitted. If SM2 is set to 1, the data appears on RxD one clock period before the falling edge on TxD, and the TxD clock then remains low for two clock periods before going high again. If SM2 is set to 0, the data appears on RxD three clock periods before the falling edge on TxD, and the TxD clock then remains low for six clock periods before going high again. This ensures that the receiving device can clock RxD data on the rising edge of TxD or when the TxD clock is low. Finally, the TI flag is set high in C1 once the last bit has been transmitted. The serial port receives data when REN is 1 and RI is zero. The TxD clock is activated, and the serial port latches data on the rising edge of the shift clock. As a result, the external device should present data on the falling edge of TxD. This process continues until all eight bits have been received. Then, after the last rising edge on TxD, the RI flag is set high in C1, which stops reception until RI is cleared by the software.
10.2 MODE 1
Mode 1 is a full-duplex, asynchronous mode. Serial communication frames are made up of ten bits transmitted on TXD and received on RXD. The ten bits consist of a start bit (0), eight data bits (LSB first), and a stop bit (1). When the W78ERD2 receives data, the stop bit goes into RB8 in SCON. The baud rate is either 1/16 or 1/32 of the Timer 1 overflow, which can be set to a variety of reload values. (The 1/16 or 1/32 factor is determined by the SMOD bit in PCON SFR.) The functional diagram is shown below.
Timer 1 Overflow Timer 2 Overflow Internal Data Bus Transmit Shift Register
STOP 2 SMOD = 0
Write to SBUF 1 0 1
16 TX START TX CLOCK
PARIN START LOAD CLOCK SOUT
TXD
TCLK
TX SHIFT TI
RCLK
0
1 16
SERIAL CONTROLLER
RX CLOCK
RI
Serial Port Interrupt
SAMPLE
1-TO-0 DETECTOR
RX START
LOAD SBUF RX SHIFT CLOCK PAROUT SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
D8
Receive Shift Register
Figure 10-2 Serial Port Mode 1
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Transmission begins when data is written to SBUF but is synchronized with the roll-over of Timer 1 (divided by 16 or 32, as configured) and not the write signal. The W78ERD2 waits until the next rollover of Timer 1 (divided by 16 or 32) before the data is put on TxD. The next bit is placed on TxD after the next rollover. After all eight bits of data are transmitted, the stop bit is transmitted. Finally, the TI flag is set, at the tenth rollover after the write signal. Reception is enabled only if REN is high. The W78ERD2 samples the RxD line at a rate of 16 times the selected baud rate, looking for a falling edge. When a falling edge is detected on the RxD pin, Timer 1 (divided by 16 or 32) is immediately reset to align the bit boundaries better, and the serial port starts receiving data. The 16 states of the counter effectively divide the time into 16 slices, and bit detection is done on a best-of-three basis using the eighth, ninth and tenth states. If the start bit is invalid (1), reception is aborted, and the serial port resumes looking for a falling edge on RxD. If the start bit is valid, the eight data bits are shifted in. Then, if (1) RI = 0 and (2) SM2 = 0 or the stop bit = 1, the stop bit is put into RB8, the data is put in SBUF, and RI is set. Otherwise, the received frame may be lost. In the middle of the stop bit, the W78ERD2 resumes looking for falling edges on RxD.
10.3 MODE 2
Mode 2 is a full-duplex, asynchronous mode. Serial communication frames are made up of eleven bits transmitted on TXD and received on RXD. The eleven bits consist of a start bit (0), eight data bits (LSB first), a programmable ninth bit (TB8) and a stop bit (1). The ninth bit is read into and transmitted from RB8. The baud rate is either 1/32 or 1/64 of the oscillator frequency, and the 1/32 or 1/64 factor is determined by the SMOD bit in PCON SFR. The functional diagram is shown below.
1/2 fosc
2
SMOD =
TB8
Write to SBUF 1
Internal Data Bus
D8 STOP PARIN START LOAD CLOCK
SOUT
TXD
0
TX START
16 16 SAMPLE
1-TO-0 DETECTOR
TX CLOCK
TX SHIFT
Transmit Shift Register
TI
SERIAL CONTROLLER RX CLOCK RX START
RI
Serial Port Interrupt Read SBUF
CLOCK PAROUT
LOAD SBUF RX SHIFT SBUF RB8
RXD
BIT DETECTOR
SIN
D8
Internal Data Bus
Receive Shift Register
Figure 10-3 Serial Port Mode 2
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W78ERD2/W78ERD2A
Transmission begins when data is written to SBUF but is synchronized with the roll-over of the counter (divided by 32 or 64, as configured) and not the write signal. The W78ERD2 waits until the next rollover of the counter (divided by 32 or 64) before the data is put on TxD. The next bit is placed on TxD after the next rollover. After all nine bits of data are transmitted, the stop bit is transmitted. Finally, the TI flag is set, at the eleventh rollover after the write signal. Reception is enabled only if REN is high. The W78ERD2 samples the RxD line at a rate of 16 times the selected baud rate, looking for a falling edge. When a falling edge is detected on the RxD pin, the counter (divided by 32 or 64) is immediately reset to align the bit boundaries better, and the serial port starts receiving data. The 16 states of the counter effectively divide the time into 16 slices, and bit detection is done on a best-of-three basis using the eighth, ninth and tenth states. If the start bit is invalid (1), reception is aborted, and the serial port resumes looking for a falling edge on RxD. If the start bit is valid, the rest of the bits are shifted in. Then, if (1) RI = 0 and (2) Either SM2 = 0 or the received 9th bit = 1, the ninth bit is put into RB8, the data is put in SBUF, and RI is set. Otherwise, the received frame may be lost. In the middle of the stop bit, the W78ERD2 resumes looking for falling edges on RxD.
10.4 MODE 3
Mode 3 is similar to mode 2 in all respects, except that the baud rate is programmable the same way it is programmable in mode 1. The functional diagram is shown below.
Timer 1 Overflow Timer 2 Overflow
STOP
TB8 Write to SBUF Internal Data Bus
D8 PARIN START LOAD CLOCK SOUT
2 SMOD = 0
TXD
1 0 1
16 TX START TX CLOCK TX SHIFT TI
TCLK
Transmit Shift Register
RCLK
0
1 16
SERIAL CONTROLLER
RX CLOCK RX START
RI
Serial Port Interrupt
SAMPLE
1-TO-0 DETECTOR
LOAD SBUF RX SHIFT CLOCK PAROUT SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
D8
Receive Shift Register
Figure 10-4 Serial Port Mode 3
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
10.5 Framing Error Detection
A frame error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically, the frame error is due to noise or contention on the serial communication line. The W78ERD2 has the ability to detect framing errors and set a flag which can be checked by software. The frame error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051 family. However, in the W78ERD2 it serves a dual function and is called SM0/FE. There are actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is accessed. When SMOD0 is set to 0, then the SM0 flag is accessed. The FE bit is set to 1 by the hardware but must be cleared by software. Once FE is set, any frames received afterwards, even those without any errors, do not clear the FE flag. The flag has to be cleared by software. Note that SMOD0 must be set to 1 while reading or writing to FE.
10.6 Multi-Processor Communications
Multi-processor communication makes use of the 9th data bit in modes 2 and 3. In the W78ERD2, the RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware feature eliminates the software overhead required in checking every received address and greatly simplifies the software programmer task. In multi-processor communication mode, the address bytes are distinguished from the data bytes by the 9th bit, which is set high for address bytes. When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the target slave (or slaves). All the slave processors should have their SM2 bit set high when waiting for an address byte. This ensures that they are interrupted only by the reception of an address byte. The automatic address recognition feature ensures that only the addressed slave is actually interrupted because the address comparison is done by the hardware, not the software. The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0, the slave is interrupted on the reception of every single complete frame of data. The unaddressed slaves are not affected, as they are still waiting for their address. The Master processor can selectively communicate with groups of slaves by using the Given Address. All the slaves can be addressed together using the Broadcast Address. The addresses for each slave are defined in the SADDR and SADEN registers. The slave address is an eight-bit value specified in the SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives the user flexibility to address multiple slaves without changing the slave address in SADDR. The following example shows how the user can define the Given Address to address different slaves.
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W78ERD2/W78ERD2A
Slave 1: SADDR 1010 0100 SADEN 1111 1010 Given Slave 2: SADDR 1010 0111 SADEN 1111 1001 Given 1010 0xx1 The Given address for slaves 1 and 2 differ in the LSB. For slave 1, it is a don't-care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010 0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 3 position is don't-care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical OR of the SADDR and SADEN SFRs. The zeros in the result are defined as don't cares. In most cases, the Broadcast Address is FFh. In the previous example, the Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2. The SADDR and SADEN SFRs are located at addresses A9h and B9h, respectively. On reset, these registers are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX XXXX(i.e. all bits don't care). This effectively removes the multi-processor communications feature, since any selectivity is disabled. 1010 0x0x
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
11. PROGRAMMABLE COUNTER ARRAY (PCA)
The PCA is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. Each module can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to p1.3 (CEX0), module 1 to p1.4 (CEX1), and so on.
Module0 Module1 PCA Timer/Counter
CH CL
16-bit Up-Counter
P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4
Module2 Module3 Module4
time base for PCA modules Module Functions: 16-bit Capture 16-bit Timer/Compare 16-bit High Speed Output 8-bit PWM Watchdog Timer (Module 4 Only)
Figure 11-1 Programmable Counter Array (PCA)
Each module has a special function register CCAPMn, where n is the same number as the module (CCAPM0 for module0, CCAPM1 for module1, etc.). CCAPMn contains the bits that control the mode of each module.
CCAPMn: PCA module compare/capture register
CCAPM0(DAH) , CCAPM1(DBH) , CCAPM2(DCH) , CCAPM3(DDH), CCAPM4(DEH)
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Reserved Enable Comparator. ECOMn = 1 enables the comparator function Capture Positive. CAPPn = 1 enables positive-edge capture. Capture Negative. CAPNn = 1 enables negative-edge capture. Match. When MATn = 1 a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set and, if ECCFn is set, generating an interrupt. Toggle. When TOGn = 1 a match of the PCA counter with this module's compare/capture register causes the CEXn bit to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn bit to be used for pulse-width modulated output. Enable CCF interrupt. Enables the compare/capture flag CCFn in the CCON register to generate an interrupt.
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W78ERD2/W78ERD2A
MODULE FUNCTION
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
No operation 16-bit capture by a positive edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit PWM Watchdog Timer (only in module4)
0 X X X 1 1 1 1
0 1 0 1 0 0 0 0
0 0 1 1 0 0 0 0
0 0 0 0 1 1 0 1
0 0 0 0 0 1 0 X
0 0 0 0 0 0 1 0
0 X X X X X 0 X
PCA Module Modes (CCAPMn Register)
PWM enables pulse width modulation. The TOG bit causes the output CEXn to toggle when there is a match between the PCA counter and the module's compare/capture register. The match bit MAT causes the CCF bit in the CCON register to be set when there is a match between the PCA counter and the module's compare/capture register, and the ECCF bit enables the CCF flag to generate an interrupt. The bits CAPP and CAPN determine whether positive and negative edges, respectively, are captured. The bit ECOM enables the comparator function. The PCA Timer is the common time-base for all five modules and can be programmed to select the appropriate timer source. The default value is 12 clocks (12T) per machine cycle, and 6T can also be selected by a bit in the options registers. The actual timer is then determined by the CPS1 and CPS2 bits in the CMOD SFR, as follows:
CPS1 CPS0 PCA TIMER COUNT SOURCE FOR 12T PCA TIMER COUNT SOURCE FOR 6T
0 0 1 1
0 1 0 1
Oscillator frequency / 12 Oscillator frequency / 4 Timer 0 overflow External input at ECI pin
Oscillator frequency / 6 Oscillator frequency / 2 Timer 0 overflow External input at ECI pin
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
CMOD(D9H): PCA counter mode register
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
CILD WDTE -
Counter idle control: CILD = 0 programs the PCA Counter to continue functioning in idle mode; CILD = 1 programs it to stop in idle mode. Watchdog Timer Enable: WDTE = 0 disables the Watchdog Timer function in PCA module 4. WDTE = 1 enables it. Reserved Reserved Reserved PCA Count Pulse Select bit 1 PCA Count Pulse Select bit 0 PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables the interrupt.
CPS1 CPS0 ECF
There are three additional bits in the CMOD SFR. CILD allows the PCA to stop during idle mode, WDTE enables and disables the watchdog function executed in module 4, and ECF causes an interrupt when the PCA timer overflows (and the PCA overflow flag CF is set). The CCON SFR contains the run-control bit for the PCA and the flags for the PCA timer overflow (CF) and each module match / capture (CCFn).
CCON(D8H): PCA counter control register
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF generates an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn on the PCA counter. Must be cleared by software to turn the PCA counter off. Reserved PCA Module4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
The CR bit (CCON.6) must be set by the software, and the PCA is turned off by clearing this bit. The CF bit (CCON.7) is set when the PCA Counter overflows, and an interrupt is generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. CCON.0~CCON.4 are the
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W78ERD2/W78ERD2A
flags for the modules and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software. The next five sections provide more information about each of the five modes (four modes for all registers and the watchdog timer in module 4).
11.1 PCA Capture Mode
To use one of the PCA modules in capture mode, either one or both of the CCAPM bits CAPN and CAPP for that module must be set.
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON(D8H) PCA INTERRUPT To CCFn CEXn Capture PCA Timer/Counter
CH
CL
CCAPnH
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPnL
CCAPMn, n=0~4 (DAH~DEH)
0
0
0
0
Figure 11-2 PCA Capture Mode
In capture mode, the external CEXn input is sampled for a transition. When a valid transition occurs, the PCA hardware loads the value of the PCA counter registers CH and CL into the module's capture registers (CCAPnH and CCAPnL). If the CCFn (CCON) and ECCFn (CCAPMn) bits are set, then an interrupt is generated.
11.2 16-bit Software Timer Comparator Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the CCAPMn register.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
CCON(D8H) PCA INTERRUPT
CCAPnH
Write To CCAPnL Write To CCAPnH
CCAPnL
To CCFn
16-bit Comparator
0 1 Enable
Match
CH
CL
PCA Timer/Counter
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n=0~4 (DAH~DEH)
0
0
0
0
Figure 11-3 PCA 16-bit Timer Comparator Mode
In this mode, the PCA timer is compared to the module's capture registers. When a match occurs, an interrupt is generated if the CCFn (CCON) and ECCFn (CCAPMn) bits are set.
11.3 High Speed Output Mode
To activate this mode, the TOG, MAT, and ECOM (CCAPMn) bits must be set.
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON(D8H) PCA INTERRUPT To CCFn
CCAPnH
Write To CCAPnL Write To CCAPnH
CCAPnL
16-bit Comparator
0 1 Enable
Match CEXn
CH
CL
PCA Timer/Counter
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n=0~4 (DAH~DEH)
0
0
1
0
Figure 11-4 PCA High Speed Output Mode
In this mode, the CEXn output toggles each time a match occurs between the PCA counter and the module's capture registers.
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W78ERD2/W78ERD2A
11.4 Pulse Width Modulator Mode
The PWM and ECOM (CCAPM) bits must be set to enable the PWM mode.
CCAPnH
CCAPnL
0 Enable
8-BIT COMPARATOR
CL < CCAPnL CEXn CL >= CCAPnL 1
Overflow
CL
CCAPMn, n=0~4 (DAH~DEH)
PCA Timer/Counter
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
0
0
0
0
0
Figure 11-5 PAC PWM Mode
All of the modules have the same frequency because they share the same PCA timer. The duty cycle of each module, however, is independently controlled by the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in CCAPLn, the output is low; when it is equal to or greater than the value in CCAPLn, the output is high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn.
11.5 Watchdog Timer
The Watchdog Timer is a free-running timer that serves as a system monitor. It is implemented in module 4, which can still be used for other modes if the Watchdog Timer is not needed.
CIDL WDTE CPS1 CPS0 ECF CMOD(D9H)
CCAP4H
Write To CCAP4L Write To CCAP4H
CCAP4L
Module4
16-bit Comparator
0 1 Enable
Match
RESET
CH
CL
PCA Timer/Counter
ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4
CCAPM4(DEH)
0
0
1
x
0
x
Figure 11-6 PCA Watchdog Timer Mode
The program first loads a 16-bit value into the compare registers. Then, like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match occurs, an internal reset is generated, but it does not make the RST pin go high.
Publication Release Date: February 14, 2007 Revision A10
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W78ERD2/W78ERD2A
12. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT)
The WDT is intended as a way to recover when the CPU may be subject to software problem. The WDT consists of a 14-bit counter and the WDT reset (WDTRST) register located at 0A6H. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to WDTRST. Once the WDT is enabled, it increments every machine cycle, while the oscillator is running, and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The program must reset the counter by writing 01EH and 0E1H to WDTRST before the WDT counter reaches 3FFFH (i.e., overflows). If it does overflow, it drives a HIGH pulse on the RST-pin. This pulse width is 98 source clocks in 12-clock mode or 49 source clocks in 6-clock mode. No external pull-down resistor or pull-up capacitor is required on the reset pin. The WDT counter cannot be read or written. To make the best use of the WDT, the WDT should be reset in sections of code that are periodically executed in time to prevent a WDT reset.
13. DUAL DPTR
The dual DPTR structure is the way the chip specifies the address of an external data memory location. There are two 16-bit DPTR registers that address external memory. The DPS bit (AUXR1, bit 0) switches between them, and it can be toggled quickly by an INC AUXR1 instruction. (AUXR1, bit 2 cannot be written and is always read as a zero, so the INC AUXR1 instruction does not affect the GF2 bit that is higher in the AUXR1 register.) It is important to keep track of the value of the DPS bit. For example, procedures and functions should save the DPS bit before switching between DPTR0 and DPTR1 and restore the original value afterwards to prevent other code from using the wrong memory.
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W78ERD2/W78ERD2A
14. TIMED-ACCESS PROTECTION
The W78ERD2 has features like Timer clock selecting by setting CKCON, software reset and ISP function that are crucial to the proper operation of the system. Consequently, The SFR CHPCON and CKCON, which control the functions, have restricted write access to protect CPU from errant operation. The W78ERD2 provides has a timed-access protection scheme that controls write access to critical bits. In this scheme, protected bits have a timed write-enable window. A write is successful only if this window is active; otherwise, the write is discarded. The write-enable window is opened in two steps. First, the software writes 87h to the register CHPENR. This starts a counter, which expires in three machine cycles. Then, if the software writes 59h to CHPENR before the counter expires, the writeenable window is opened for three machine cycles. After three machine cycles, the window automatically closes, and the procedure must be repeated again to access protected bits. The suggested code for opening the write-enable window is CHPENRREG 0F6h MOV CHPENR, #87h MOV CHPENR, #59h Five examples, some correct and some incorrect, of using timed-access protection are shown below. ; Define new register CHPENR, located at 0F6h
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W78ERD2/W78ERD2A
Example 1: Valid access MOV CHPENR, #87h MOV CHPENR, #59h MOV CKCON, #00h ;3 M/C, Note: M/C = Machine Cycles ;3 M/C ;3 M/C
Example 2: Valid access MOV CHPENR, #87h MOV CHPENR, #59h NOP SETB EWT ;3 M/C ;3 M/C ;1 M/C ;2 M/C
Example 3: Valid access MOV CHPENR, #87h MOV CHPENR, #59h ORL CKCON, #01h ;3 M/C ;3 M/C ;3M/C
Example 4: Invalid access MOV CHPENR, #87h MOV CHPENR, #59h NOP NOP CLR MD ;3 M/C ;3 M/C ;1 M/C ;1 M/C ;2 M/C
Example 5: Invalid Access MOV CHPENR, #87h NOP MOV CHPENR, #59h SETB MD ;3 M/C ;1 M/C ;3 M/C ;2 M/C
In the first three examples, the protected bits are written before the window closes. In Example 4, however, the write occurs after the window has closed, so there is no change in the protected bit. In Example 5, the second write to CHPENR occurs four machine cycles after the first write, so the timed access window in not opened at all, and the write to the protected bit fails.
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W78ERD2/W78ERD2A
15. IN-SYSTEM PROGRAMMING (ISP) MODE
The W78ERD2 is equipped with 64 KB of main flash EPROM (AP Flash EPROM) for the application program and 4 KB of auxiliary flash EPROM (LD Flash EPROM) for the loader program. In normal operation, the microcontroller executes the code in the AP Flash EPROM. If the code in the AP Flash EPROM needs to be modified, however, the W78ERD2 allows the program to activate the In-System Programming (ISP) mode to modify it. The contents in the AP Flash EPROM can be modified by setting the CHPCON register. The CHPCON is read-only by default. The program must write two specific values, 87H and then 59H, sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with any other values disables the write attribute. Setting the bit CHPCON.0 makes the W78ERD2 enter ISP mode when it wakes up from the next idle mode. It takes time to set this up in idle mode, however, so the program may use a timer interrupt to wake up the W78ERD2 and enter ISP mode after an appropriate amount of time in idle mode. To change the contents in the AP Flash EPROM, the existing contents must set the CHPCON register and then enter idle mode. When the W78ERD2 wakes up, it switches from AP Flash EPROM to LD Flash EPROM, clears the program counter, pushing 0000H to the first 2 bytes of stack memory and executes the interrupt service routine in the LD Flash EPROM. Therefore, the first execution of RETI instruction will make the program jump to 00H in the LD Flash EPROM. When the AP Flash EPROM has been updated, the W78ERD2 offers a software reset to switch back to the AP Flash EPROM. Setting CHPCON bits 0, 1 and 7 to logic-1 creates a software reset to reset the CPU. A flowchart for the LD Flash EPROM program is shown at the end of this section.
SFRAH, SFRAL: The objective address of the on-chip flash EPROM in ISP mode. SFRFAH contains the high-order byte, and SFRFAL contains the low-order byte. SFRFD: The program data in ISP mode. SFRCN: The control byte for ISP mode.
SFRCN (C7)
BIT NAME FUNCTION
7 6 5 4 3, 2, 1, 0
WFWIN OEN CEN CTRL[3:0]
Reserve. On-chip flash EPROM bank select for in-system programming. 0: 64-KB flash EPROM bank is the destination for re-programming. 1: 4-KB flash EPROM bank is the destination for re-programming. Flash EPROM output enable. Flash EPROM chip enable. Flash EPROM control signals; see below.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
MODE
WFWIN
CTRL<3:0>
OEN
CEN
SFRAH, SFRAL
SFRFD
Erase 64KB AP Flash EPROM Program 64KB AP Flash EPROM Read 64KB AP Flash EPROM Erase 4KB LD Flash EPROM Program 4KB LD Flash EPROM Read 4KB LD Flash EPROM
0 0 0 1 1 1
0010 0001 0000 0010 0001 0000
1 1 0 1 1 0
0 0 0 0 0 0
X Address in Address in X Address in Address in
X Data in Data out X Data in Data out
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W78ERD2/W78ERD2A
The Algorithm of In-System Programming
Part 1:APROM START
procedure of entering In-System Programming Mode
Enter In-System Programming Mode ? (conditions depend on user's application) Yes
No
Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H
Execute the normal application program
Setting Timer (about 1.5 us) and enable timer interrupt
END
Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode)
CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program.
Go
Figure 15-1 The algorithm of ISP for AP ROM
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Part 2: 4KB LDROM
Go Procedure of Updating the 64KB APROM
Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM
Is F04KBOOT Mode? (CHPCON.7=1) No
Yes End of Programming ?
Yes
No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Is currently in the F04KBOOT Mode ? No Software reset CPU and re-boot from the 64KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Yes
Get the parameters of new code
Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) (Address and data bytes) through I/O ports, UART or other interfaces.
Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM)
Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H
Start Timer and enter IDLE Mode. (Erasing...)
Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in H/W reboot Mode)
End of erase operation. CPU will be wakened by Timer interrupt.
END
Executing new code from address 00H in the 64KB APROM.
PGM
Figure 15-2 The algorithm of ISP for LD ROM
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W78ERD2/W78ERD2A
16. H/W REBOOT MODE (BOOT FROM LDROM)
By default, the W78ERD2 boots up from the AP Flash EPROM after a power-on reset. Sometimes, this is not desirable. H/W REBOOT mode forces the W78ERD2 to use the LD Flash EPROM instead and execute in-system programming procedures. Enter H/W REBOOT mode using these settings.
H/W REBOOT MODE
P4.3 P2.7 P2.6 OPTION BIT MODE
X L
L X
L X
Bit4 = L Bit5 = L
H/W REBOOT H/W REBOOT
This might be implemented by connecting pins P2.6 and P2.7 to switches or jumpers. For example, in a CD-ROM system, P2.6 and P2.7 might be connected to the PLAY and EJECT buttons on the panel. If the user wants to enter H/W REBOOT mode, the user can press these two buttons at the same time and then turn on the power to force the W78ERD2 to enter H/W REBOOT mode. After the power-on, releasing both buttons finishes the in-system programming procedure. This mode can be accidentally activated, so be careful with the values of pins P2, P3, ALE, EA and PSEN at reset.
The Reset Timing For Entering H/W REBOOT Mode 1 P2.7
Hi-Z
P2.6
Hi-Z
RST 10us 20ms
H/W REBOOT Mode 2 P4.3 Hi-Z
RST 10us 20ms
Figure 16-1
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
17. OPTION BITS REGISTER
In the on-chip Flash EPROM writer programming mode mode, the flash EPROM can be programmed and verified repeatedly. Until the code is ready, it can be protected by properly setting option bits. Option bits control the initial configuration of W78ERD2, including code protection, system clock mode selection (6T/12T), H/W reboot mode selection and oscillator control.
Lock bit
This bit is used to protect the code in the W78ERD2. It may be set after the programmer finishes programming and verifies the sequence. Once this bit is set to logic-0, both the Flash EPROM data and Option Bits Register cannot be accessed again.
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W78ERD2/W78ERD2A
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent a MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic-0, a MOVC instruction in external program memory space can only access code in external memory, not in internal memory. A MOVC instruction in internal program memory can always access both internal and external memory. If this bit is logic-1, there are no restrictions on MOVC.
Encryption
This bit is used to enable and disable the encryption logic for code protection. Once encryption is enabled, the data presented on port 0 is encoded via encryption logic. This bit can be reset only by erasing the whole chip.
Oscillator Control
The gain of the on-chip oscillator amplifier can be reduced by bit B7 in the option bits register. If bit 7 is set to zero, the gain is cut in half. According the circuit in Figure 20-1, the values of R, C1 and C2 may need some adjustment when running at lower gain. Furthermore, reducing the gain by one-half may improperly affect an external crystal running at frequencies above 25 MHz.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
18. ELECTRICAL CHARACTERISTICS
18.1 Absolute Maximum Ratings
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply Input Voltage Operating Temperature Storage Temperature
VDD - VSS VIN TA TST
-0.3 VSS -0.3 0 -55
+6.0 VDD +0.3 70 +150
V V
C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
18.2 D.C. Characteristics
(VDD - VSS = 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4]
VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL[*4] VIL1 VIL2 VIL3
4.5 -50 0 -10 -500 0 0 0
5.5 20 10 10 +10 +300 +10 0.8 0.8 0.8
V mA mA
A A A A A
No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0< VIN V V V
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W78ERD2/W78ERD2A
D.C. Electrical Characteristics, continued
PARAMETER
SYM.
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1[*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN Sink Current P1, P3, P4 Sink Current P0, P2, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN Source Current P1, P2, P3, P4 Source Current P0, P2, ALE, PSEN
Notes: *1. RST pin is a Schmitt-trigger input.
[*3] [*3]
VIH1 VIH2 VIH3 VOL1 VOL2 Isk1 Isk2 VOH1 VOH2 Isr1 Isr2
2.4 3.5 3.5 4 10 2.4 2.4 -180 -8
VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.45 8 15 -300 -12
V V V V V mA mA V V
A
VDD = 5.5V VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V VIN = 0.45V VDD = 4.5V VIN = 0.45V VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A VDD = 4.5V VIN = 2.4V VDD = 4.5V VIN = 2.4V
mA
*2. P0, ALE and PSEN are tested in external-access mode.
*3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
18.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 ns variation.
Clock Input Waveform
XTAL1
T CH F OP, TCP T CL
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed Clock Period Clock High Clock Low
Notes:
Fop TCP TCH TCL
0 25 10 10
-
40 -
MHz ns ns ns
1 2 3 3
1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low
TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW
1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP-
2 TCP 3 TCP
2 TCP 1 TCP 1 TCP -
ns ns ns ns ns ns ns ns
4 1, 4 4 2 3
PSEN Low to Data Valid
Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width
PSEN Pulse Width
Notes:
4 4
1. P0.0 - P0.7, P2.0 - P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 ns.
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W78ERD2/W78ERD2A
Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
ALE Low to RD Low
RD Low to Data Valid
TDAR TDDA TDDH TDDZ TDRD
3 TCP- 0 0 6 TCP-
6 TCP
3 TCP+ 4 TCP 2 TCP 2 TCP -
ns ns ns ns ns
1, 2 1
Data Hold from RD High Data Float from RD High
RD Pulse Width
Notes:
2
1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
ALE Low to WR Low Data Valid to WR Low Data Hold from WR High
WR Pulse Width
TDAW TDAD TDWD TDWR
3 TCP- 1 TCP- 1 TCP- 6 TCP-
6 TCP
3 TCP+ -
ns ns ns ns
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE
TPDS TPDH TPDA
1 TCP 0 1 TCP
-
-
ns ns ns
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
19. TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA TDAR TDDA TDDH, TDDZ
PORT 0 RD TDRD
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W78ERD2/W78ERD2A
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
T DWD
T DAW
T DWR
Port Access Cycle
S5 XTAL1
S6
S1
ALE TPDS PORT INPUT SAMPLE TPDH T PDA DATA OUT
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
20. TYPICAL APPLICATION CIRCUITS
20.1 External Program Memory and Crystal
V DD
31 19 10 u R
CRYSTAL
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
18 9
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 21 22 23 24 25 26 27 28 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND
3 4 7 8 13 14 17 18 1 11
D0 D1 D2 D3 D4 D5 D6 D7 OC G
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
12 13 14 15 1 2 3 4 5 6 7 8
74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 GND 20 22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure 20-1
CRYSTAL
C1
C2
R
6 MHz 16 MHz 24 MHz 32 MHz 40 MHz
47P 30P 15P 10P 1P
47P 30P 15P 10P 1P
6.8K 3K
Above table shows the reference values for crystal applications.
Notes:
1. For C1, C2 and R components, see Figure 20-1 2. The crystal should be as close as possible to the XTAL1 and XTAL2 pins on the application board.
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W78ERD2/W78ERD2A
20.2 Expanded External Data Memory and Oscillator
v DD
VDD OSCILLATOR 31 19 18 8.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8 10 u EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 OC G 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND 20 22 27
Figure 20-2
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
21. PACKAGE DIMENSIONS
40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.254 3.81 0.406 1.219 0.203 3.937 4.064 0.457 0.559 1.27 1.372 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
0.254 0.356 52.20 52.58
0.610 14.986 15.24 15.494 0.550 0.110 0.140 15 0.670 0.090 13.72 2.286 3.048 0 16.00 16.51 13.84 2.54 3.302 13.97 2.794 3.556 15 17.01 2.286
1 S A A2 L B B1 e1
20 E c A1
eA S
Notes:
Base Plane Seating Plane
eA
a
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.590 0.590 0.680 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658
Dimension in mm Min. Nom. Max.
4.699 0.508 3.683 0.66 0.406 0.203 16.46 16.46 14.99 14.99 17.27 17.27 2.296 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71 16.00 16.00 17.78 17.78 2.794 0.10
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27
BSC
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W78ERD2/W78ERD2A
44-pin PQFP
HD D
44 34
Dimension in inch
Dimension in mm
Symbol
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 y L L1 Detail F
Seating Plane
See Detail F
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
22. APPLICATION NOTE
22.1 In-System Programming (ISP) Software Examples
This application note illustrates the in-system programmability of the Winbond W78ERD2 Flash EPROM microcontroller. In this example, the microcontroller boots from 64 KB AP Flash EPROM bank and waits for a key to enter ISP mode to re-program the 64-KB AP Flash EPROM. While in ISP mode, the microcontroller executes the loader program in the 4-KB LD Flash EPROM. The loader program erases the 64-KB AP Flash EPROM and then reads the new code from an external SRAM buffer (or through other interfaces) to update the 64-KB AP Flash EPROM.
EXAMPLE 1:
;******************************************************************************************************************* ;* Example of 64K AP Flash EPROM program: Program will scan the P1.0. If P1.0 = 0, enters ;* in-system Programming mode for updating the content of AP Flash EPROM code else executes the ;* current ROM code. ;* XTAL = 40 MHz ;******************************************************************************************************************* .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU BFH F6H C4H C5H C6H C7H
ORG 0H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG 00BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 64K AP Flash EPROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A, P1 ; SCAN P1.0 ANL A, #01H CJNE A, #01H, PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE JMP NORMAL_MODE PROGRAM_64K: MOV CHPENR, #87H MOV CHPENR, #59H MOV CHPCON, #03H MOV TCON, #00H MOV IP, #00H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE ; TR = 0 TIMER0 STOP ; IP = 00H
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W78ERD2/W78ERD2A
MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TMOD, #01H MOV TCON, #10H MOV PCON, #01H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ; TL0 = F0H ; TH0 = FFH ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ; PROGRAMMABILITY
;******************************************************************************** ;* Normal mode 64KB AP Flash EPROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . . . . ; User's application program
EXAMPLE 2:
;***************************************************************************************************************************** ;* Example of 4KB LD Flash EPROM program: This loader program will erase the 64KB AP Flash EPROM first, ;* then reads the new code from external SRAM and program them into 64KB AP Flash EPROM bank. ;* XTAL = 40MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H BFH F6H C4H C5H C6H C7H
; JUMP TO MAIN PROGRAM
;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 4KB LD Flash EPROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_4K: MOV SP, #C0H ; BE INITIAL SP REGISTER
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE. MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE. MOV A, CHPCON ANL A, #80H CJNE A, #80H, UPDATE_64K; CHECK H/W REBOOT MODE ? MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE MOV TCON, #00H MOV TMOD, #01H MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TCON, #10H MOV PCON, #01H UPDATE_64K: MOV CHPENR, #00H MOV TCON, #00H MOV IP, #00H MOV IE, #82H MOV TMOD, #01H MOV R6, #3CH MOV R7, #B0H MOV TL0, R6 MOV TH0, R7 ERASE_P_4K: MOV SFRCN, #22H MOV TCON, #10H MOV PCON, #01H ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED
; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE
; DISABLE CHPCON WRITE-ATTRIBUTE ; TCON = 00H, TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 ms. DEPENDING ; ON USER'S SYSTEM CLOCK RATE.
; SFRCN(C7H) = 22H ERASE 64K ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE (FOR ERASE OPERATION)
;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN, #0H ; READ 64KB AP Flash EPROM MODE MOV SFRAH, #0H ; START ADDRESS = 0H MOV SFRAL, #0H MOV R6, #FBH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER 0 MOV PCON, #01H ; ENTER IDLE MODE MOV A, SFRFD ; READ ONE BYTE CJNE A, #FFH, BLANK_CHECK_ERROR INC SFRAL ; NEXT ADDRESS MOV A, SFRAL JNZ BLANK_CHECK_LOOP
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W78ERD2/W78ERD2A
INC SFRAH MOV A, SFRAH CJNE A, #0H, BLANK_CHECK_LOOP ; END ADDRESS = FFFFH JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1, #F0H MOV P3, #F0H JMP $ ;******************************************************************************* ;* RE-PROGRAMMING 64KB AP Flash EPROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE MOV R2, #00H ; TARGET LOW BYTE ADDRESS MOV R1, #00H ; TARGET HIGH BYTE ADDRESS MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K) MOV R6, #5AH ; SET TIMER FOR PROGRAMMING, ABOUT 50 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 PROG_D_64K: MOV SFRAL, R2 ; SFRAL(C4H) = LOW BYTE ADDRESS MOVX A, @DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER MOV SFRFD, A ; SFRFD(C6H) = DATA IN MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO MOV PCON, #01H ; ENTER IDLE MODE (PRORGAMMING) INC DPTR INC R2 CJNE R2, #0H, PROG_D_64K INC R1 MOV SFRAH, R1 CJNE R1, #0H, PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB AP Flash EPROM BANK ;***************************************************************************** MOV R4, #03H ; ERROR COUNTER MOV R6, #FBH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV DPTR, #0H ; The start address of sample code MOV R2, #0H ; Target low byte address MOV R1, #0H ; Target high byte address MOV SFRAH, R1 ; SFRAH, Target high address MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE) READ_VERIFY_64K: MOV SFRAL, R2
; SFRAL(C4H) = LOW ADDRESS
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO MOV PCON, #01H INC R2 MOVX A, @DPTR INC DPTR CJNE A, SFRFD, ERROR_64K CJNE R2, #0H, READ_VERIFY_64K INC R1 MOV SFRAH, R1 CJNE R1, #0H, READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR, #87H ; CHPENR = 87H MOV CHPENR, #59H ; CHPENR = 59H MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET. ERROR_64K: DJNZ R4, UPDATE_64K . . . .
; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
22.2 How to Use Programmable Counter Array
Please go to Winbond's website at http://www.winbond.com.tw fort the application note.
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W78ERD2/W78ERD2A
23. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3 A4
June 2004 August 2004 Sep. 30, 2004 April 20, 2005
38 74 38 72 4 17 22 38 49 3 32 46
Initial Issued Modify the content of PCA Add the application of PCA Add Enhanced full duplex serial port with framing error detection and automatic address recognition Add Important Notice To add Lead Free part No. of packages. Correct GF3 to GF2 in AUXR1 Correct XICONH Add Programmable Timers/Counters. Re-organize document. Add a section of timed-access protection Remove block diagram Remove all Leaded package parts Correct the interrupt vector of INT2 & INT3. Correct CMOD(D8h) to CMOD(D9h)
A5
June 2, 2005
A6 A7 A8 A9 A10
Sep. 5, 2005 October 2, 2006 December 4, 2006 December 15, 2006 February 14, 2007
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Publication Release Date: February 14, 2007 Revision A10
W78ERD2/W78ERD2A
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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